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The design of robust electrostatic discharge (ESD) protections of microcircuits is one of the major issues in microelectronics. The coupling of electrostatic discharges to integrated circuits results in high-current transients, which may lead to the failure of the device as a consequence of thermal runaway phenomena within the semiconductor. The development of appropriate predictive simulation tools to ensure the necessary level of robustness for the device requires an accurate characterization of the main physical parameters of silicon up to local temperatures approaching the melting point. This goal has been pursued in the framework of the Europe an research project DEMAND, where the impact ionization coefficient (IIC), the bulk mobility, and the surface mobility of electrons and holes in silicon have been measured up to temperatures, which have never been reached before. The dedicated test structures selected for the measurement of the multiplication factor were Static Inductance Transistors (SIT, see inset in Figure 1), Bipolar Junction Transistors (BJT), and Vertical DMOS transistors all designed to cover a large interval of the electrical field.
Figure 1 shows the (electron) current collected at the gate of a p-SIT, which arises due to the impact generation and carrier separation along the channel. These data are used to calibrate the compact model for the IIC of holes as a function of the electric field and of the temperature. The University of Bologna model (UNIBO) for the IIC of electrons calibrated up to a temperature of 773 K and extrapolated to a temperature of 1000 K is presented in Figure 2. This model has been validated for fields in the 40-500 kV/cm range. The maximum temperature, which can be reached by these test structuresis limited by the dominance of thermal carrier generation over impact generation. The operating range of conventional junction-isolated van der Pauw structures for the characterization of the Hall carrier mobility in silicon as a function of the temperature is limited to 400 K by several parasitic effects.
This limit can be extended up to about 700 K by a proper design of the structures and by the application of a reverse bias to the isolating junction. Nonetheless, alternative structures are needed to reach the temperature range of interest. Figure 3 shows the measurement up to 973 K of the Hall bulk mobility of electrons carried out by unipolar van der Pauw structures using a dedicated metallization scheme. Figure 4 shows the improvements in the prediction of the snap-back behavior of an ESD diode submitted to reverse transmission line pulses, when using the newly calibrated electron impact ionization model.
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 Fig. 1 The measurement of the gate current of the p-SIT (inset) as a function of the drain voltage is used to extract the IIC of holes as a function of the temperature |
 Fig. 2 IIC of electrons as a function of the electric field implemented according to the Bologna model calibrated with the present measurements |
 Fig. 3 Comparison of the measured bulk mobility of electrons for different doping concentrations (symbols) with the UNIBO model (red lines) prior to calibration |
 Fig. 4 Measurement and simulation of the characteristics of an ESD diode submitted to a reverse high-voltage pulse from the breakdown to the thermal failure. With the newly calibrated model (UNIBO), the prediction is correct up to 1200 K |
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